Feasibility analysis of hardware acceleration for AML

Algebraic Machine Learning (AML) offers new opportunities in terms of transparency and control. However, that comes along with many challenges regarding software and hardware implementations. To understand the hardware needs of this new method it is essential to analyze the algorithm and its computational complexity. With this understanding, the final goal of this microproject is to investigate the feasibility of various hardware options particularly in-memory processing hardware acceleration for AML.

Output

Simulation model for a PIM architecture using AML

Report

Presentations

Project Partners:

• Algebraic AI S.L., Fernando Martin Maroto
• Technische Universität Kaiserslautern (TUK), Christian Weis
• German Research Centre for Artificial Intelligence (DFKI), Matthias Tschöpe

Primary Contact: FERNANDO MARTIN MAROTO, Algebraic AI

Main results of micro project:

We have carried out a theoretical study of the AML sparse crossing algorithm efficiency and identified in-memory processing and FPGA combined with in-memory processing as the two feasible options for Algebraic Machine Learning. Currently, we are working on a prototype implementation that involves FPGA and in-memory processing of bit arrays in commercial Upmem RAM memories.

Contribution to the objectives of HumaneAI-net WPs

This work is critical to speed up the calculation of Algebraic Machine Learning models and in so doing contribute to:
1- Bidirectional human-machine communication using formal expressions
2- Possibility to set goals and establish limits via formal constraints
3- Reduced dependency on statistics can help overcome bias
4- Transparency by design
5 -Possibility for decentralized, cooperative distributed machine learning

Tangible outputs

• Program/code: AML engine prototype using bitarrays – Fernando Martin Maroto
  www.algebraic.ai